library ieee;
use ieee.std_logic_1164.all;

entity decoder38_2_34 is
    port(a, b, c, en: in std_logic;
         y: out std_logic_vector(7 downto 0));
end decoder38_2_34;

architecture behav of decoder38_2_34 is
    signal indata: std_logic_vector(2 downto 0);
begin
    indata <= a & b & c;
    process(indata, en)
    begin
        if(en = '0') then
            case indata is
                when "000"=>y<="11111110";
                when "001"=>y<="11111101";
                when "010"=>y<="11111011";
                when "011"=>y<="11110111";
                when "100"=>y<="11101111";
                when "101"=>y<="11011111";
                when "110"=>y<="10111111";
                when "111"=>y<="01111111";
                when others =>y<="ZZZZZZZZ";
            end case;
        else
			y<="11111111";
        end if;
    end process;
end behav;
